The invention relates generally to computer systems and deals more particularly with a digital circuit and method for rapidly calculating the logarithm of a number.
The calculation of a logarithm in prior art computer systems is often based on software implementations of a mathematical algorithm for the calculation of a logarithm, such as power series expansion. Other computer systems rely on storage of large tables of logarithms.
In some prior art computer systems the calculation of a logarithm is sped up by the employment of a floating point unit or a mathematical coprocessor. However even the fastest state of the art floating point units available, such as the Intel-processor 80387, require about one hundred machine cycles for calculating the logarithm of a floating point number. In scientific or technical applications the calculation of logarithms is required frequently, so that a reduction of the number of machine cycles required for calculating a logarithm significantly enhances the performance in these cases.
From the IBM Technical Disclosure Bulletin, Volume 11, No. 8, January 1969, pp. 914, an algorithm for finding logarithms of binary numbers to the base 2 is known. Only shift operations and at most a one-add need to be performed to find the logarithm. However the accuracy of the logarithmation is limited to four binary digits according to this algorithm.
A similar method and a device for logarithmic representation of binary numbers in analog form is described in Instruments and Experimental Techniques, Volume 29, No. 3, pt. 1, page 630-1. This device comprises a logarithmic converter in which the mantissa of the logarithm is obtained from the values of several significant bits of a binary number with the aid of a table stored in read-only memory. The obtained codes are then put into analog form by a digital to analog converter.
From DE-A-3 622 205 a digital circuit for logarithmic signal processing is known. The integrated circuit comprises a comparator array logic having a plurality of interconnected comparators arranged in an array. This approach is costly in terms of the hardware needed for its realization.
From DE-A-3 030 124 method and apparatus for logarithmic calculations are known. This method only provides for a rough approximation of the logarithm of a number, which is not sufficient in most applications.
From an article entitled "Fast Logarithmic D.A. Conversation with Small Error" in Electronics Letters, 19th February 1976, Volume 12, No. 4, pp. 100, a technique for the conversion of floating-point digital numbers to the corresponding logarithmic analog values is known. This technique is based on the division of the mantissa into two parts. The more significant part of the mantissa is decoded by a logarithmic decoder logic having a number of inputs corresponding to the number of digits in the more significant part of the mantissa. The major drawback of this technique is the expense necessary in terms of hardware, restriction to a predefined number of digits and a relatively low degree of accuracy.
It is therefore an object of the invention, to provide an improved digital circuit and method for calculating the logarithm of a number.
In particular the invention is aimed to reduce the number of machine cycles needed to calculate a logarithm with a high degree of accuracy.